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SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

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PRELIMINARY DATA<br />

206 <strong>SH</strong>debug link<br />

dm_clkout<br />

dm_osync<br />

dm_out[3:0]<br />

A<br />

B<br />

C<br />

Start and end of messages<br />

Output-idle words are transmitted over the <strong>SH</strong>debug link during times when the<br />

debug module has no data to send, for example, when the DM FIFO is empty.<br />

When the FIFO contains several trace messages, they are sent over the <strong>SH</strong>debug<br />

link with a minimum of one idle (4-<strong>bit</strong>) word separating the messages.<br />

Output-idle words serve another purpose; as the means of telling the tool the status<br />

of the debug module DBUS receive buffer. See Section : Flow control of messages<br />

from tool on page 205.<br />

Message structure<br />

A B C<br />

Figure 8: Debug-link output<br />

A B C<br />

output-idle state, DM_OUT[2:0] = 0B000,<br />

DM_OUT[3] = <strong>SH</strong>-5 DBUS receive buffer busy (1) or empty (0)<br />

start of message, DM_OUT[2:0] = message type<br />

message data<br />

The values signalled on dm_out[2:0] when DM_OSYNC is asserted are defined in First<br />

word of message on page 118.<br />

D R A FT<br />

Table 72 and Table 73 provide some examples of DTRC and DBUS packets as they<br />

appear on the <strong>SH</strong>debug link, and give details of the meaning assigned to DM_OUT[3]<br />

during non-idle transmissions.<br />

<strong>SuperH</strong>, Inc.<br />

<strong>SH</strong>-5 <strong>System</strong> <strong>Architecture</strong>, <strong>Volume</strong> 3: Debug 05-SA-10003 v1.0

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