SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
28 Key concepts
1.2.10 Performance counters
SH-5 provides a series of performance counters, these are used in conjunction with
the WP channels and WP facilities to provide observation of internal CPU and bus
events. Some of the counters are physically located within the WPC and others are
physically located within the debug module.
• Performance counters within the WPC may be incremented either when a WPC
watchpoint hit occurs or when a WPC_PERF channel match occurs. Refer to
Section 1.18: WP channel type WPC_PERF on page 165.
• Performance counters within the DM may be incremented when a PL watchpoint
hit occurs.
An implementation may provide a maximum of 16 performance counters, thus a 4
bit field is used for the performance counter ID. The counter has a maximum size of
64 bits.
Any particular implementation may provide fewer than 16 counters, and those
provided may have fewer than 64 bits. See Section 4.1.3: Performance counters on
page 243 for implementation-specific details.
The counters may be written to at any time. They are modulo-N counters, and thus
will wrap around.
D R A FT
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug 05-SA-10003 v1.0