SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
WP channel type PL 193
Debug interrupt action registers
In addition to the generic DM.WP_PLX_ACTION registers, the following registers
provide additional functions associated with bus analyzer debug interrupts.
DM.WP_PLx_EXCTRL
where x = channel id
Field Bits Size Volatile? Synopsis Type
CBUF_FREEZE 0 1 ✓ Capture buffer status/freeze control RW
Operation
When read
When written
HARD reset 0
Controls the bus analyzer capture buffer when debug interrupt is
enabled. This register is set by hardware following a PL
watchpoint hit when debug interrupt is enabled. Debug event
handling software should read the contents of the capture buffer,
and then finally clear the CBUF_FREEZE register.
If PL debug interrupt is not enabled, the contents of this register
are undefined.
Returns 0 when the capture buffer is empty, 1 when it is frozen
following a watchpoint hit resulting in a debug interrupt.
Provides a write-1-clear function for clearing the capture buffer
frozen state.
Value - Description
0: no action.
1: clears the CBUF_FREEZE register if it had previously been set by
hardware. No action if debug interrupt is not enabled or if this
register is already clear.
— [63:1] 63 — Reserved RES
Operation
Reserved
When read Returns 0
When written
HARD reset 0
D R A FT
Ignored
Table 68: DM.WP_PLx_EXCTRL register definition
05-SA-10003 v1.0
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug