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SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

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PRELIMINARY DATA<br />

Watchpoint channels 43<br />

DM.WP_nx_PRE<br />

where<br />

n= {IA/OA/IV},<br />

x = channel ID (relative to N)<br />

Field Bits Size Volatile? Synopsis Type<br />

ASID_ENABLE 1 1 — ASID match enable RW<br />

Operation<br />

When read<br />

When written<br />

HARD reset<br />

The WPC.WP_NX_ PRE register determines the inclusion of the<br />

current ASID value in the debug event match.<br />

The field defined here is not involved in the debug event match,<br />

it determines whether the ASID value is placed into trace<br />

messages.<br />

Value - Description<br />

0: include the ASID value (at the point of the trigger) in the trace<br />

message.<br />

1: do not include ASID value in trace message.<br />

Returns current value<br />

Updates value<br />

Undefined<br />

— [63:2] 62 — Reserved RES<br />

Operation<br />

Reserved<br />

When read Returns 0<br />

When written<br />

HARD reset 0<br />

Ignored<br />

Table 15: DM.WP_{IA/OA/IV}x_PRE register definition<br />

D R A FT<br />

05-SA-10003 v1.0<br />

<strong>SuperH</strong>, Inc.<br />

<strong>SH</strong>-5 <strong>System</strong> <strong>Architecture</strong>, <strong>Volume</strong> 3: Debug

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