SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
Key concepts 19
1.2.5 Debug module
The debug module manages:
• The SHdebug link and the debug interface to the JTAG TAP controller.
Provides a connection to the SuperHyway bus, and also a route to extract trace
information.
• The DM_TRIN_N and the DM_TROUT_N pins.
• An on-chip FIFO (known as the DM FIFO).
This acts as a temporary buffer for trace messages. Trace messages from the DM
FIFO can be dealt with as follows:
- Sent to the selected debug interface, JTAG or SHdebug link. If trace
messages are generated faster than they can be transferred to the selected
debug interface, either the CPU can be stalled or new trace messages can be
discarded.
- Accumulated in the DM FIFO until it fills. Once the DM FIFO fills, either the
CPU can be stalled or new trace messages are discarded. In this mode,
memory-mapped registers allow the DM FIFO contents to be read.
- Old messages in the DM FIFO overwritten by new ones so that the DM FIFO
contains the most recent trace messages generated. In this mode,
memory-mapped registers allow the DM FIFO contents to be read.
- Written to an area of the target system’s RAM (known as a trace buffer).
• Trace buffer
One of the available destinations for trace messages is to write these into an
area of target system memory allocated as a trace buffer. Debug module register
fields set the size and the base address of this trace buffer area. The size can set
between 64 Kbytes and 64 Mbytes.
D R A FT
The trace buffer can operate in two different ways:
- As circular buffer, with old entries being overwritten by new entries once the
buffer fills. The buffer always contains the most recent trace messages.
- As a fixed length buffer which does not wrap around. Once the buffer fills,
trace messages are discarded which means that the buffer contains the
earliest trace messages.
05-SA-10003 v1.0
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug