SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
Reset, panic and debug events 79
Note:
The MMU bit of the status register determines whether the MMU is enabled. The
standard exception handler launch sequence involves copying the status register
(SR) to the saved status register (SSR). Therefore the previous enable/disable status
of the MMU is available such that it can be restored by the exception handler’s exit
sequence (that is, the RTE instruction).
SR.BL bit
When the BL bit of SR is ‘1’:
• Attempts to raise a debug exception of type DEBUGIA, DEBUGIV, DEBUGOA,
DEBUGSS or BREAK will result in a panic event being raised instead. EXPEVT will
be set to indicate the normal event type, even though a panic event is generated.
This allows the panic handler to distinguish between the synchronous debug
event types.
Panic events can be recovered from (as the previous EXPEVT contents are
recorded in PEXPEVT), thus a target debug agent will need to handle both panic
events and other types of debug event.
• Attempts to raise a debug interrupt (DEBUGINT) will block until the BL bit is
cleared.
If the cause of the debug interrupt is de-asserted whilst BL is set, the debug interrupt
will be lost.
SR.WATCH bit
See Section 1.6.1: SR.WATCH bit on page 66.
SR.STEP bit
When SR.STEP is ‘1’, an event will be raised whenever an instruction execution
completes. The type of event generated depends on the value of SR.BL:
D R A FT
• If SR.BL is ‘0’, a debug exception of type DEBUGSS will be raised.
• If SR.BL is ‘1’, a panic event will be raised.
In both these cases EXPEVT is set as per Table 26: Synchronous debug exceptions on
page 81
05-SA-10003 v1.0
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug