SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
DBUS protocol 229
This means that the transaction ID field in the DBUS message has no useful
function since there can never be more than one outstanding transaction. However,
checking of the TID in the response is still performed by the SuperHyway initiator
and the tool must ensure that the TID in the response message generated by the tool
is identical to the TID in request message received from SH-5.
3.6.4 Unsolicited responses
Undefined effects will occur if a tool sends an unsolicited DBUS response to the
SH-5.
3.6.5 Critical word ordering
For multiple data phase transactions (that is, Load16, Store16, Load32, Store32),
the address on the SuperHyway request bus is the address of the first data word of
the transaction. The burst address ordering is linear. Burst requests issued by the
MMU/cache are always critical-word-first and the low order bits of the address
determine the word order of Store requests and of Load responses as shown in
Table 79 and Table 80 below.
Address bits[0, 3]
0b0xxx 0, 1
0b1xxx 1, 0
Address bits[0,4]
Table 79: Word order for Store16, Load16
Word order
0b00xxx 0, 1, 2, 3
0b01xxx 1, 2, 3, 0
Word order
D R A FT
0b10xxx 2, 3, 0, 1
0b11xxx 3, 0, 1, 2
Table 80: Word order for Store32, Load32
05-SA-10003 v1.0
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug