SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
66 WP channel matching
1.6 WP channel matching
The following subsections and diagram explain how watchpoint channel matching is
achieved. Where:
PRE = precondition register (WPC or DM as appropriate),
ACTION = action register (WPC or DM as appropriate).
1.6.1 SR.WATCH bit
The SR.WATCH bit is used to enable or disable all actions related to WPC-based WP
channels (IA, OA, IV, BR, WPC_PERF) in both the WPC and the DM. It has no effect
on the other WP channels (BRK, FPF, PL, DM).
If SR.WATCH is ‘0’, all the action conditions (Section 1.5: Debug event actions on
page 48) associated with all the WPC-based WP channels defined above are
disabled. Thus these channel’s actions which would normally launch the event
handler, affect event/performance counters, chain latches, trigger out pins or
generate trace for example, will be voided.
SR.WATCH is automatically cleared to ‘0’ by the hardware when launching a reset,
panic or debug event handler. This allows all instructions executed within the event
handler to be invisible to the debug system itself in order to prevent generation of
unwanted trace, and to prevent the CPU from trying to launch a debug exception
during the execution of the event handler itself.
This may appear to be a nontypical situation (that is, breakpoints would not be set
in the debug event handler code), but unexpected exceptions might occur due to
“wide” programming of IA/OA and particularly IV watchpoint channels.
Event handler software should re-enable action conditions by restoring SR.WATCH to
‘1’ when leaving its critical region. This is achieved using the RTE instruction to
write the contents of the saved status register (SSR) to the status register (SR). This
will not result in the BR channel triggering for the branch caused by the RTE
instruction, as the state of SR.WATCH is considered at the start of an RTE
instruction’s execution (see WP channel type BR on page 156).
D R A FT
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug 05-SA-10003 v1.0