SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
Trigger functions 225
Write DEBUG reset opcode to
WPC.CPU_CTRL_ACTION
NORMAL
Normal speed
DM_CLKOUT
‘n’ clocks
IN_RESET
3.5 Trigger functions
NORMAL
Slow speed
DM_CLKOUT
Reset operation
completes
(‘n’ is approximately
10 PP-bus cycles)
STATUS0/
STATUS1
signals
CPU fetching
instructions
DM_CLKOUT
Figure 15: DEBUG reset (via write to WPC.CPU_CTRL_ACTION)
SH-5 provides a trigger-in (DM_TRIN_N) and a trigger-out pin (DM_TROUT_N). These
allow external analysis hardware (such as a logic analyzer) to control and monitor
specific watchpoints.
The trigger out pin can also be configured to provide external visibility of timing
events (such as interrupt latency), and to detect internal states (such as trace buffer
overflow).
D R A FT
Refer to Section 1.8.10: DM.TRCTL (trace/trigger register) on page 97 for details of
the control register fields that determine the functions of the trigger-in and
trigger-out pins.
05-SA-10003 v1.0
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug