SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
180 SuperHyway watchpoint comparators
The SuperHyway bus may be implemented with multiple bus segments to improve
performance by permitting transactions to occur on multiple segments concurrently.
In such a multi-segment implementation, the SuperHyway bus analyzer will be
physically implemented with multiple watchpoint comparators, one set on each
segment. Functionally however, watchpoint sets on multiple bus segments are
treated as a single set, controlled by the same registers.
SuperHyway bus analyzer watchpoints include the standard WP channel features,
and so can make use of chain-latches, event counters, performance counters:
• Chain-latches can be used to combine arbitrary WP channels in sequence
(including combining CPU and bus analyzer watchpoints).
• Event counters can be used to provide “trigger after N hits” functionality.
Accesses from the CPU to the WPC memory-mapped registers (resulting from loads
and stores in the instruction stream) may be routed internally to the CPU,
bypassing the SuperHyway. Whether this happens is implementation-dependent.
Hence, whether such loads and stores can be detected by the bus analyzer channels
is implementation-dependent.
Accesses to the WPC registers from other SuperHyway modules (for example, the
SHdebug link via the debug module) are visible to the bus analyzer channels.
2.2 SuperHyway watchpoint comparators
Control registers associated with each SuperHyway watchpoint allow the following
SuperHyway specific parameters to be defined:
• Bus transaction type: Opcode value and opcode mask fields allow any type of
request or response to be matched.
• Source device ID (specific ID or any source).
• Destination device ID (top 8-bits of address, maskable).
D R A FT
• Destination address comparison range, for requests only.
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug 05-SA-10003 v1.0