SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
244 Scalable parameters
Chain-latch
ID (4-bits)
Latch name
There is not global connectivity for the ACTION_CHAIN_ALTER actions between the
WPC and DM based WP channels. Thus, the appropriate registers must be used to
achieve this effect - for a WPC channel to alter a DM chain latch, the WPC channel’s
DM.WP_NX_ACTION.ACTION_CHAIN_ALTER field and the CHAIN_ID fields are used (the
channel’s WPC.WP_NX_ACTION.ACTION_CHAIN_ALTER field should be set to not alter a
chain-latch).
Chain-latch latency
Pre-condition for WPC
watchpoints
Pre-condition for
DM and bus
analyzer
watchpoints
Due to inter-module delays, not all chain latches change state immediately upon the
detection of a watchpoint hit. Table 88 specifies the latency for each of the
chain-latch groups.
D R A FT
Changeable by
watchpoint hits
0x0 WPC.IA0_CHAIN OA, IV, WPC_PERF FPF, BR, PL Auto by IA0
0x1 WPC.IA1_CHAIN OA, IV, WPC_PERF FPF, BR, PL Auto by IA1
0x2 WPC.IA2_CHAIN OA, IV, WPC_PERF FPF, BR, PL Auto by IA2
0x3 WPC.IA3_CHAIN OA, IV, WPC_PERF FPF, BR, PL Auto by IA3
0x8 WPC.CHAIN_0 IA, OA, IV, WPC_PERF FPF, BR, PL IA, OA, IV
0xC DM.CHAIN_0 IA, OA, IV, WPC_PERF FPF, BR, PL IA, OA, IV, PL
0xF DM.CHAIN_TRIG_IN IA, OA, IV, WPC_PERF FPF, BR, PL, IA, OA, IV, PL
All other
values
undefined
Table 87: SH-5 evaluation device chain latch IDs
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug 05-SA-10003 v1.0