SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
WP channel type BR 157
DM.WP_BR_FILTER
0x100028
Field Bits Size Volatile? Synopsis Type
BASIC_ENABLE 0 1 — Enable RW
See basic_enable field of Table 14 on page 38.
ASID_ENABLE 1 1 — ASID match enable RW
Operation
When read
When written
HARD reset
Enables or disables the inclusion of the current ASID value in
the debug event match, and determines whether an ASID field
appears in BR trace messages.
Value - Description
0: ASID match disabled. Thus the ASID value at the point of
trigger will be included in BR trace messages.
1: ASID match enabled. Will only trigger when the current ASID
matches the ASID_VALUE field, thus ASID value will not be
included in BR trace messages.
Returns current value
Updates value
Undefined
CHAIN_ENABLE 2 1 — Chain-latch enable RW
See the CHAIN_ENABLE field of Table 14 on page 38.
CHAIN_ID [6:3] 4 — Chain-latch ID RW
See the CHAIN_ID field of Table 15 on page 42
D R A FT
ASID_VALUE [14:7] 8 — ASID match value RW
SR_MD_
ENABLE
See the ASID_VALUE field of Table 14 on page 38
[16:15] 2 — CPU user/privileged mode selection RW
See the SR_MD_ENABLE field of Table 14 on page 38
See Section 1.14.3: Precondition checking for events and RTE on page 161
regarding precondition checks for SR_MD_ENABLE when tracing events and RTE.
Table 58: DM.WP_BR_FILTER register definition
05-SA-10003 v1.0
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug