SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
Key concepts 27
If multiple WP channels are setup to affect the same event counter, only a single
event counter decrement will be performed for each simultaneous channel match
(rather than the alternative of performing one decrement per simultaneous WP
channel match).
Register description
{WPC/DM}.ECOUNT_VALUE_x
where
x = event counter ID
Field Bits Size Volatile? Synopsis Type
VALUE [63:0] 64 ✓ Counter value RW
Operation
When read
When written
HARD reset
Contains the counter’s value.
The implementation defines the significant size of the counter
(known as ECOUNT.SIZE, see Section 4.1.2: Event counters on
page 242).
Bits [0:(ECOUNT.SIZE-1)] count down when a WP channel is set
to decrement this counter. When the counter value reaches zero,
no further decrementing occurs. Even if a watchpoint PRE
register has an event counter enabled, debug software can
disable the counter by setting the value to zero.
Bits [ECOUNT.SIZE, 63] are undefined.
Returns current value
Updates value
Undefined
Table 7: {WPC/DM}.ECOUNT_VALUE_x register definition
D R A FT
05-SA-10003 v1.0
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug