SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
Debug module 89
When in “trace link”, “DM FIFO trace hold” or “trace buffer hold” mode the trace
system can be programmed to either stall the CPU, or discard trace messages (see
Stall/discard overview on page 91). In the FIFO modes, trace messages are packed
into the DM FIFO in an implementation defined manner, according to the size of the
trace message:
• Some DM FIFO implementations may be byte-based so that a variant number of
trace messages can be held in the DM FIFO, this provides “best fit” and thus
makes most efficient use of the available FIFO space.
• Some DM FIFO implementations may pack trace entries in a fixed manner (that
is, 3*64-bit) intervals.
In normal operation, fields of trace messages corresponding to PC values or bus
analyzer address values are encoded relative to the last such address in order to
make the trace messages as compact as possible. If the trace message which
“seeded” these values is lost, the subsequent trace messages using relative values
cannot be interpreted until a further absolute value is issued in a subsequent trace
message.
For this reason, when in “DM FIFO trace hold”/“trace buffer hold” mode or “circular
DM FIFO”/“circular trace buffer” mode, all trace messages use absolute rather than
relative values to ensure that the trace messages can be utilized even when a
preceding message which “seeded” these values has been lost. See Section
: Encoding of address offsets on page 120 for full details.
Trace messages can be read from the DM FIFO an entry at a time using the
DM.FIFO_{0/1/2} registers (see Section 1.8.13: DM.FIFO_0/DM.FIFO_1/DM.FIFO_2
(FIFO port register) on page 112). When the DM FIFO is in “circular DM FIFO” mode,
care must be taken to ensure trace is not being generated whilst it is being extracted
or trace messages may be lost. See Section 1.8.13: DM.FIFO_0/DM.FIFO_1/
DM.FIFO_2 (FIFO port register) on page 112 for full details.
D R A FT
05-SA-10003 v1.0
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug