SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
SHdebug link 203
3.2.5 Pin state during reset
Three pins are sampled during a reset sequence initiated externally to the SH-5
through NOTRESETP or NOTRESETM. These pins allow the following to be determined
as part of the external reset sequence:
• debug module to be enabled or disabled.
The signal used is referred to as DM_ENABLE. It is obtained by sampling the
DM_CLKIN pin during reset.
• CPU to be brought up in a suspended or running state.
The signal used is referred to as SUSPEND. It is obtained by sampling the DM_ISYNC
pin during reset.
• Reset to be forced to be a DEBUG reset, rather than the normal POWERON or MANUAL
reset specified by the RESETP and RESETM pins.
The signal used is referred to as RESET_MODE. It is obtained by sampling the
DM_IN pin during reset.
The pins are not sampled in this way when a reset is generated by the watchdog
timer or from software (see Section 1.3.2: Control operations on page 31 and
Section 1.7: Reset, panic and debug events on page 73).
Section 3.4.2: Reset functions available from debug tools on page 219 defines the
reset sequence in detail. Further information is available in the PMU chapter
(Refer to the reset controller chapter in Volume 1.).
D R A FT
05-SA-10003 v1.0
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug