25.02.2015 Views

SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

SHOW MORE
SHOW LESS

Create successful ePaper yourself

Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.

PRELIMINARY DATA<br />

196 WP channel type PL<br />

DM.WP_PLx_CBDATA<br />

where x = channel id<br />

Note that when the PLx channel is not enabled,<br />

the contents of all fields of this register are<br />

undefined.<br />

Field Bits Size Volatile? Synopsis Type<br />

PLINK_DATA [63:0] <strong>64</strong> ✓ <strong>SuperH</strong>yway transaction data RO<br />

Event specifics<br />

Source<br />

Reason<br />

Operation<br />

When read<br />

When written<br />

HARD reset<br />

<strong>SuperH</strong>yway<br />

Undefined behavior<br />

This register provides access to the data word captured in the<br />

bus analyzer capture buffer following a watchpoint hit when<br />

debug interrupt is enabled.<br />

Returns current value<br />

Ignored<br />

Undefined<br />

Table 70: DM.WP_PLx_CBDATA register definition<br />

Occurrence of a <strong>SuperH</strong>yway bus transaction which matches<br />

according to the PL channel’s comparator settings.<br />

Writing to DM.WP_PLX_* (except DM.WP_PLX_PRE) when the WP channel is enabled is<br />

undefined.<br />

Supported fields in DM.WP_PLx_PRE:<br />

D R A FT<br />

BASIC_ENABLE, ECOUNT_ENABLE, ECOUNT_ID, CHAIN_ENABLE, CHAIN_ID<br />

<strong>SuperH</strong>, Inc.<br />

<strong>SH</strong>-5 <strong>System</strong> <strong>Architecture</strong>, <strong>Volume</strong> 3: Debug 05-SA-10003 v1.0

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!