SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
DBUS protocol 237
Store32
Request
OPC[7:0]
ADDR[31:0]
SRC[7:0]
TID[7:0]
MSK0[7:0]
DATA0[63:0]
MSK1[7:0]
DATA1[63:0]
MSK2[7:0]
DATA2[63:0]
MSK3[7:0]
DATA3[63:0]
Response
R_OPC[7:0]
R_SRC[7:0]
R_TID[7:0]
Opcode Store32 (0x52).
Address, where ADDR[31:24] identifies the module.
ADDR[23:5] specifies the offset within the module.
ADDR[4:3] specifies the address of the critical word within a 32
byte quantity (see Section 3.6.5: Critical word ordering on
page 229).
ADDR[2:0] is not significant.
Source identifier, defined by the system not the module.
Transaction identifier, defined by the module not the system.
Byte significance within word (‘1’ == significant, ‘0’ == not
significant).
See Table 81: DBUS mask/address mapping for big and little
endian modes on page 230.
First 8 byte quantity to write.
As MSK0 but for DATA1 rather than DATA0.
Second 8 byte quantity to write.
As MSK0 but for DATA2 rather than DATA0.
Third 8 byte quantity to write.
As MSK0 but for DATA3 rather than DATA0.
Fourth 8 byte quantity to write.
D R A FT
Response type, either 0x80 for Success, or 0x81 for Failure.
Copy of SRC.
Copy of TID.
05-SA-10003 v1.0
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug