SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
166 WP channel type WPC_PERF
The counter is incremented a bounded number of cycles after the watchpoint hit or
the CPU state occurred. The bounded time is fixed, and thus allows timing
relationships between CPU states to be observed.
If SR.WATCH is ‘0’, WPC_PERF channels will not trigger.
1.18.1 Match registers
WPC.WP_WPC_PERFx_MATCH_TYPE
where x = channel ID
Field Bits Size Volatile? Synopsis Type
ITLB_MISS 0 1 — Instruction TLB miss RW
Operation
When read
When written
HARD reset
Instruction fetch access failed (due to a lack of an instruction
TLB translation).
Results in either 0 or 1 increments per instruction.
Returns current value
Updates value
Undefined
ICACHE_ACCESS 1 1 — Instruction Cache Access RW
Operation
When read
When written
HARD reset
An instruction fetch successfully hit the Instruction cache.
This includes preload accesses (due to PT instructions), and
cache coherency (ICBI) accesses, but excludes prefetches
(PREFI).
Results in either 0 or 1 increments per instruction.
Returns current value
Updates value
D R A FT
Undefined
Table 60: WPC.WP_WPC_PERFx_MATCH_TYPE register definition
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug 05-SA-10003 v1.0