SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...
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SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

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PRELIMINARY DATA<br />

Debug register address map 257<br />

Register name Offset References<br />

WPC.WP_IA0_MATCH_START 0x400010 Table 50: WPC.WP_IAx_MA<br />

TCH_START register<br />

definition on page 139<br />

WPC.WP_IA0_MATCH_END 0x400018 Table 51: WPC.WP_IAx_MA<br />

TCH_END register definition<br />

on page 140<br />

WPC.WP_IA1_PRE 0x400040 See cross references for<br />

channel WP_IA0.<br />

WPC.WP_IA1_ACTION<br />

0x400048<br />

WPC.WP_IA1_MATCH_START<br />

WPC.WP_IA1_MATCH_END<br />

WPC.WP_IA2_PRE<br />

WPC.WP_IA2_ACTION<br />

WPC.WP_IA2_MATCH_START<br />

WPC.WP_IA2_MATCH_END<br />

WPC.WP_IA3_PRE<br />

WPC.WP_IA3_ACTION<br />

WPC.WP_IA3_MATCH_START<br />

WPC.WP_IA3_MATCH_END<br />

0x400050<br />

0x400058<br />

0x400080<br />

0x400088<br />

0x400090<br />

0x400098<br />

0x4000C0<br />

0x4000C8<br />

0x4000D0<br />

0x4000D8<br />

Table 94: Register map and references<br />

D R A FT<br />

05-SA-10003 v1.0<br />

<strong>SuperH</strong>, Inc.<br />

<strong>SH</strong>-5 <strong>System</strong> <strong>Architecture</strong>, <strong>Volume</strong> 3: Debug

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