SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
Address comparison 183
2.4 Address comparison
For multiple data phase transactions (Load16/Load32 and Store16/Store32) the
address on the SuperHyway request bus is the address of the first data word of the
transaction. The burst address ordering is linear. Burst requests issued by the
MMU/Cache are always critical-word-first and bits [4:3] of the address determine
the word order of Store requests and of Load responses as shown in Table 62 and
Table 63.
Address Bits [3,4]
00 0, 1, 2, 3
01 1, 2, 3, 0
10 2, 3, 0, 1
11 3, 0, 1, 2
Word Order
Table 62: SuperHyway word order for Store32, Load32
Address Bit [3]
0 0, 1
1 1, 0
Word Order
Table 63: SuperHyway word order for Store16, Load16
Since the request contains a single address corresponding to the first word of the
transaction, the SuperHyway bus analyzer computes the implied address of each
subsequent data phase.
D R A FT
05-SA-10003 v1.0
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug