SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
Debug/trace
architecture
1.1 Overview of debug features
D R A FT
1
The SH-5 debug system provides both traditional CPU debug, and advanced CPU
and system debug features.
A number of different features are available, the number of instances is scalable on
a per-implementation basis. A brief overview of these debug features is given below.
In the following description of debug features, the term ‘tool’ refers to any form of
software development system, typically consisting of a computer plus a debug
adaptor or emulator.
1.1.1 Communication with a tool
SH-5 provides two interfaces through which it can communicate with a software
development tool; a dedicated high-speed interface (called the SHdebug link) and a
JTAG interface. A tool can use only one of these interfaces at a time.
The SHdebug link is the preferred debug interface as communications between a
tool and SH-5 is much faster using the SHdebug link rather than JTAG. However,
some future SH-5 based ASICs may be pin-limited and not have enough pins
available for a SHdebug link interface. The JTAG interface allows a tool to
communicate with SH-5 and have access to all the on-chip debug features described
in this document but at a substantially reduced performance compared with that
offered by the SHdebug link. In addition to being used for system debug, the JTAG
interface can also be used for its normal functions of boundary scan and internal
scan.
05-SA-10003 v1.0
SH-5 System Architecture, Volume 3: Debug