SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
5
1.8.11 DM.TRBUF (trace buffer register) 107
1.8.12 DM.TRPTR (trace pointer register) 110
1.8.13 DM.FIFO_0/DM.FIFO_1/DM.FIFO_2 (FIFO port register) 112
1.8.14 DM.PC (shadow program counter register) 117
1.9 Debug protocols and interfaces 118
1.9.1 Endianness 118
1.9.2 Overall message structure 118
1.9.3 DTRC messages 119
1.9.4 DBUS messages 136
1.10 WP channel type BRK 136
1.10.1 Match registers 137
1.10.2 Event specifics 137
1.11 WP channel type IA 139
1.11.1 Match registers 139
1.11.2 Address comparison 141
1.11.3 SHcompact behavior 141
1.11.4 Event specifics 141
1.12 WP channel type OA 143
1.12.1 Match registers 143
1.12.2 Address comparison 145
1.12.3 Data match registers 147
1.12.4 SHcompact behavior 149
1.12.5 Interrupt action 150
1.12.6 Event specifics 150
1.13 WP channel type IV 152
D R A FT
1.13.1 Match registers 153
1.13.2 SHcompact mode 154
1.13.3 Event specifics 154
1.14 WP channel type BR 156
1.14.1 Branch filter register 156
1.14.2 Event specifics 160
1.14.3 Precondition checking for events and RTE 161
05-SA-10003 v1.0
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug