SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
242 Scalable parameters
4.1.2 Event counters
SH-5 evaluation device provides two 16-bit event counters
0b0000
0b0001
All other values
Event counter ID (4 bits)
One event counter is implemented in the WPC (for timing critical exception
matching). This counter is only accessible to WPC implemented channels.
One event counter is implemented in the DM. This counter is only accessible to the
PL watchpoint channels.
Event counter latency
ECOUNT.SIZE = 16
WPC.ECOUNT_VALUE_0
DM.ECOUNT_VALUE_0
Undefined
Table 85 shows the latency for the event counters.
Event counter name
Name
Table 84: SH-5 evaluation device event counter Ids
Delay from WPC watchpoint hit (CPU
cycles)
For use in
precondition
check
For use in
subsequent
counter update
Delay from Bus
Analyzer
watchpoint hit (DM
cycles)
WPC.ECOUNT_VALUE_X 4 1 Not applicable
D R A FT
DM.ECOUNT_VALUE_X Not applicable Not applicable TBD
Table 85: Update latency for event counters
The latency for WPC.ECOUNT_VALUE_X means that the new value is visible between 1
and 4 instructions after the one that hits a WPC channel and causes the change in
value. Put another way, between 0 and 3 following instructions will use the old value
of WPC.ECOUNT_VALUE_X in their precondition checks. The actual number of
instructions involved depends on whether stalls occur in the pipeline (for example,
due to resource or operand dependencies, or delays in instruction fetching).
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SH-5 System Architecture, Volume 3: Debug 05-SA-10003 v1.0