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SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

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PRELIMINARY DATA<br />

<strong>SH</strong>debug link 201<br />

3.2.2 Protocol levels<br />

The <strong>SH</strong>debug link has two protocol levels in each direction:<br />

• A low-level protocol which provides start-of-message indication, end-of-message<br />

indication and flow control. At this level, message input and message output are<br />

completely independent and messages can flow in both directions at the same<br />

time.<br />

• A higher-level protocol which identifies the message contents and specifies the<br />

response required to each request. Certain message types, that is, trace<br />

messages from <strong>SH</strong>-5 are output-only and require no response from the tool.<br />

The protocol is encoded little endian.<br />

3.2.3 External pins<br />

The <strong>SH</strong>debug link interface pins are described in Table 71.<br />

Signal Lines Type<br />

Internal<br />

pull-up<br />

Description<br />

DM_CLKIN 1 IN_TBD Yes Clock from debug adapter, in<br />

phase with DM_IN and DM_ISYNC.<br />

DM_CLKOUT 1 OUT_TBD No <strong>SH</strong>debug link clock source.<br />

DM_OUT[0,3] 4 OUT_TBD No Output data, synchronous to the<br />

rising edge of DM_CLKOUT.<br />

DM_OSYNC 1 OUT_TBD No Output sync, synchronous to the<br />

rising edge of DM_CLKOUT.<br />

DM_IN 1 IN_TBD Yes Input data, synchronous to the<br />

rising edge of DM_CLKIN.<br />

D R A FT<br />

DM_ISYNC 1 IN_TBD Yes Input sync, synchronous to the<br />

rising edge of DM_CLKIN.<br />

DM_TRIN_N 1 IN_LVTTL Yes Trigger input.<br />

DM_TROUT_N 1 OUT_LVTTL No Trigger output.<br />

Table 71: <strong>SH</strong>debug link external pins<br />

05-SA-10003 v1.0<br />

<strong>SuperH</strong>, Inc.<br />

<strong>SH</strong>-5 <strong>System</strong> <strong>Architecture</strong>, <strong>Volume</strong> 3: Debug

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