SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
Key concepts 23
Latch name
Pre-condition
for WPC
watchpoint
WPC
watchpoint can
alter
Pre-condition
for DM and bus
analyzer
watchpoint
Bus analyzer
watchpoint can
alter
DM.CHAIN_X
Chain state
IA, OA, IV,
WPC_PERF
yes (IA, OA, IV
only)
FPF, BR, PL
Each latch has 1 bit of state. This denotes if the latch is set (1) or clear (0). The state
is affected by the WP channels.
If the state of a chain latch is being changed by conflicting conditions, for example,
being set by a watchpoint hit and being cleared by a different watchpoint hit on the
same clock cycle, then the resulting state of the chain-latch is undefined.
Chain-latches can be included in the pre-trigger and action-condition operations of
each of the watchpoint channels.
The pre-conditions of each WP channel allow the WP match to succeed only if the
specified chain latch is set.
Table 3 shows how the state of the generic chain-latches in the WPC and the DM
can be changed. Table 4 gives similar information for the IA watchpoints in the
WPC. Refer to Section 1.6: WP channel matching on page 66 for a definition of
Full-Hit.
Chain alter (see Table 18 on page 49)
Table 2: Chain-latch use
FULL_WP_HIT
(see Section 1.6: on page 66)
yes
D R A FT
New state
0bxx 0 Unchanged
0b00 or 0b01 1 Unchanged
0b10 1 Clear
0b11 1 Set
Table 3: Generic chain-latch action
05-SA-10003 v1.0
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug