SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

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PRELIMINARY DATA 260 Debug register address map DM misc. Register name Offset References DM.EXP_CAUSE 0x100010 Table 11: DM.FORCE_DEB UGINT register definition on page 34. DM.FPF 0x100018 Section 1.8.9: DM.FPF register definition on page 97. DM.PC 0x100020 Section 1.8.13: DM.FIFO_0/ DM.FIFO_1/DM.FIFO_2 (FIFO port register) on page 112. DM.WP_BR_FILTER 0x100028 Table 58: DM.WP_BR_FILT ER register definition on page 157 DM.OA_MATCH_DATAVAL 0x100030 Section 1.12.3: Data match registers on page 147 DM.OA_MATCH_ DATAMASK 0x100038 DM.FORCE_DEBUGINT 0x100088 DM.FORCE_DEBUGINT register definition on page 34. Table 94: Register map and references D R A FT SuperH, Inc. SH-5 System Architecture, Volume 3: Debug 05-SA-10003 v1.0
PRELIMINARY DATA Debug register address map 261 DM trace/FIFO control Register name Offset References DM.TRCTL 0x100040 Table 31: DM.TRCTL definition on page 97. DM.TRBUF 0x100048 Table 32: DM.TRBUF definition on page 107. DM.TRPTR 0x100050 Table 33: DM.TRPTR definition on page 111. DM.FIFO_0 0x100058 Table 35: DM.FIFO_{0/1/2} definition on page 114 DM.FIFO_1 0x100060 DM.FIFO_2 0x100068 DM.FIFO_REQ 0x100070 Table 36: DM.FIFO_REQ definition on page 115. DM.FIFO_ACK 0x100078 Table 37: DM.FIFO_ACK definition on page 116. DM.CLKOUTDIV 0x100090 Table 74: DM.CLKOUTDIV definition on page 211. Table 94: Register map and references D R A FT 05-SA-10003 v1.0 SuperH, Inc. SH-5 System Architecture, Volume 3: Debug
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PRELIMINARY DATA SuperH TM (SH) 64-
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PRELIMINARY DATA Contents Preface 9
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PRELIMINARY DATA 5 1.8.11 DM.TRBUF
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PRELIMINARY DATA 7 3.2.5 Pin state
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PRELIMINARY DATA Preface This docum
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PRELIMINARY DATA Debug/trace archit
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PRELIMINARY DATA Overview of debug
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PRELIMINARY DATA Key concepts 15 Th
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PRELIMINARY DATA Key concepts 17 Ac
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PRELIMINARY DATA Key concepts 19 1.
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PRELIMINARY DATA Key concepts 21 1.
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PRELIMINARY DATA Key concepts 23 La
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PRELIMINARY DATA Key concepts 25 {W
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PRELIMINARY DATA Key concepts 27 If
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PRELIMINARY DATA Key concepts 29 Re
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PRELIMINARY DATA CPU control 31 1.3
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PRELIMINARY DATA CPU control 33 1.3
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PRELIMINARY DATA Watchpoint channel
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PRELIMINARY DATA Debug event action
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PRELIMINARY DATA WP channel matchin
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PRELIMINARY DATA Reset, panic and d
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PRELIMINARY DATA Debug module 85 DM
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PRELIMINARY DATA Debug module 87
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PRELIMINARY DATA Debug module 89 Wh
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PRELIMINARY DATA Debug module 91 St
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PRELIMINARY DATA Debug module 93 Mu
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PRELIMINARY DATA Debug module 95 1.
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PRELIMINARY DATA Debug module 97 1.
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PRELIMINARY DATA Debug module 99 DM
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PRELIMINARY DATA Debug module 101 D
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PRELIMINARY DATA Debug module 107 1
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PRELIMINARY DATA Debug module 113
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PRELIMINARY DATA Debug module 117 1
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PRELIMINARY DATA Debug protocols an
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PRELIMINARY DATA WP channel type BR
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PRELIMINARY DATA WP channel type IA
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PRELIMINARY DATA WP channel type IA
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PRELIMINARY DATA WP channel type OA
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PRELIMINARY DATA WP channel type IV
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PRELIMINARY DATA WP channel type IV
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PRELIMINARY DATA WP channel type FP
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PRELIMINARY DATA WP channel type WP
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PRELIMINARY DATA SuperHyway bus ana
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PRELIMINARY DATA SuperHyway watchpo
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PRELIMINARY DATA Address comparison
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PRELIMINARY DATA Freezing bus maste
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PRELIMINARY DATA WP channel type PL
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PRELIMINARY DATA External debug int
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PRELIMINARY DATA SHdebug link 201 3
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PRELIMINARY DATA SHdebug link 203 3
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PRELIMINARY DATA SHdebug link 205 T
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PRELIMINARY DATA SHdebug link 207 D
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Page 213 and 214: PRELIMINARY DATA JTAG interface 213
Page 219 and 220: PRELIMINARY DATA Debug tool reset/s
Page 225 and 226: PRELIMINARY DATA Trigger functions
Page 227 and 228: PRELIMINARY DATA DBUS protocol 227
Page 241 and 242: PRELIMINARY DATA Implementation spe
Page 243 and 244: PRELIMINARY DATA Scalable parameter
Page 253 and 254: PRELIMINARY DATA Debug register add
Page 259: PRELIMINARY DATA Debug register add
Page 265 and 266: PRELIMINARY DATA Index A Actions 13
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Page 269 and 270: PRELIMINARY DATA 269 158-160, 166-1
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