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SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

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PRELIMINARY DATA<br />

84 Reset, panic and debug events<br />

DM.EXP_CAUSE<br />

0x100010<br />

Field Bits Size Volatile? Synopsis Type<br />

PL_INTERRUPT 1 1 ✓ <strong>SuperH</strong>yway watchpoint interrupt RW<br />

FORCED_DEBUG_<br />

INTERRUPT<br />

Operation<br />

When read<br />

When written<br />

HARD reset 0<br />

This field is set due to a transitory state on the <strong>SuperH</strong>yway<br />

triggering a bus analyzer watchpoint which has<br />

.ACTION_EXCEPTION set as 1.<br />

Returns current value<br />

Updates value.<br />

Writing 0 will clear the PL_INTERRUPT.<br />

Writing 1 has no effect - any pending <strong>SuperH</strong>yway interrupts<br />

will not be lost, and subsequent reads will return 1 (unless<br />

the source of the interrupt is unexpectedly removed).<br />

2 1 ✓ Forced debug interrupt RW<br />

Operation<br />

When read<br />

When written<br />

HARD reset 0<br />

Contains 1 if the debug interrupt was raised by writing ‘1’ to<br />

the DM.FORCE_DEBUGINT.FORCE register field (see Section<br />

1.3.4: on page 33).<br />

Returns current value<br />

Updates value.<br />

Writing 0 will clear the forced debug interrupt.<br />

Writing 1 has no effect - any pending forced debug interrupts<br />

will not be lost, and subsequent reads will return 1 (unless<br />

the source of the interrupt is unexpectedly removed).<br />

D R A FT<br />

Table 29: DM.EXP_CAUSE register definition<br />

<strong>SuperH</strong>, Inc.<br />

<strong>SH</strong>-5 <strong>System</strong> <strong>Architecture</strong>, <strong>Volume</strong> 3: Debug 05-SA-10003 v1.0

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