SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
176 WP channel type WPC_PERF
1.18.2 Operand cache access types
Table 60 defines four modes of operand cache access (OCACHE_ACCESS,
OCACHE_MISS, OCACHE_ALIAS, NONCACHE_ACCESS) that can be seperately counted.
The selection of which mode applies to each case is shown in Table 61. The terms
ACCESS, ALIAS and MISS mean OCACHE_ACCESS, OCACHE_ALIAS and OCACHE_MISS
respectively. The “—” symbol indicates that no performance counter trigger occurs in
that situation. For example, the GETCFG and PUTCFG instructions never increment
performance counters.
SR.MMU=1
D R A FT
SR.MMU=0
Effective address in operand cache Yes No No No N/A
Physical address in operand cache Yes Yes No No N/A
Mode
Cacheable translation Yes Yes Yes No N/A
Instruction
SHmedia LD, ST, FLD, FST ACCESS ALIAS MISS NONCACHE_ACCESS
SHcompact
LD .., R63 (prefetch) ACCESS ALIAS MISS NONCACHE_ACCESS
ALLOCO ACCESS ALIAS MISS NONCACHE_ACCESS
SWAP.Q ALIAS ALIAS MISS NONCACHE_ACCESS
OCBI, OCBP, OCBWB ALIAS ALIAS MISS NONCACHE_ACCESS
GETCFG/PUTCFG — — — —
All instructions using the
@-addressing mode with
the exclusion of JMP, JSR,
MOVA, OCBI, OCBP,
OCBWB
ACCESS ALIAS MISS NONCACHE_ACCESS
OCBI, OCBP, OCBWB ALIAS ALIAS MISS NONCACHE_ACCESS
Table 61: Operand cache access modes for performance counting
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug 05-SA-10003 v1.0