SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
12 Overview of debug features
Either debug interface provides a logical connection between a tool and the SH-5
SuperHyway bus. This logical connection gives the tool full access to the physical
address map, and all the nodes connected to the bus.
A 16 Mbyte portion of the address map is mapped to memory physically located
within the tool. Accesses to this area result in read or write messages over the
selected debug interface. These can then be handled by the tool to provide
“remote-memory” systems. By using this feature in conjunction with facilities to
stop, start and run the CPU from a specified address, ROM-less target systems are
possible during product development phases.
In addition to these download and control operations, the selected debug interface
may also be used to either spill or read-out trace information.
1.1.2 Trigger pins
SH-5 provides a trigger in (DM_TRIG_N) and a trigger out pin (DM_TROUT_N). These
allow external analysis hardware (such as a logic analyzer) to be connected.
The trigger out pin can also be configured to provide external visibility of timing
events (such as interrupt latency), and to detect internal states (such as FIFO
overflow).
1.1.3 Watchpoint detection
The CPU includes facilities to watchpoint on several events which occur in normal
code execution:
• Instruction address - for breakpoints in ROM, or ranged breakpoints.
• Operand address - to detect range-based memory writes.
• Instruction value - to perform flexible profiling and register watchpoints.
• PC branch - to perform branch tracing, call graph profiling and sample based
profiling.
D R A FT
The watchpoints can be triggered in complex manners using generic pre-conditions
to combine them in sequence, and also to combine them with event counters. The
pre-conditions also allow them be made process (ASID) and instruction mode
(SHmedia vs. SHcompact) specific.
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug 05-SA-10003 v1.0