SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
External debug
interfaces
3.1 Introduction
D R A FT
3
A development tool can communicate with SH-5’s on-chip debug functions through
one of two possible interfaces; a dedicated high-speed interface called the SHdebug
link and the JTAG interface.
The JTAG interface is controlled by the on-chip JTAG TAP controller and when
JTAG is the currently-selected debug interface, debug messages are transferred
between the TAP controller and the debug module. When the SHdebug link is the
currently-selected debug interface, the debug module directly controls all SHdebug
link functions.
Other pins provide trigger-in and trigger-out signals which allow some of the debug
functions to be monitored and controlled by a logic analyzer or other external test
equipment.
Refer to Chapter 1: Debug/trace architecture on page 11 for a description of the
debugging functions incorporated into SH-5.
05-SA-10003 v1.0
SH-5 System Architecture, Volume 3: Debug