SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
86 Debug module
• Bus capture buffers in the SuperHyway bus analyzers.
Trace bus from
SuperHyway bus
analyzer
Trace bus from
WPC in core
Watchpoint
trigger signals
from WPC in
core and bus
Analyzers
bus
capture
Capture
buffer
CPU core
clock
Determine
latch/counter
action
Chain
latches
Event
counters
Performance
counters
Trigger
latch &
pulse
generator
Select
FIFO for
compressed
messages
Write to
Memory
Function
Pre-scaler
Create trace
message
SuperHyway
Slave
Figure 3: Debug module functions
D R A FT
The debug module has the following main functions:
Time reference
counter (40-bit)
Time difference
counter (8-bit)
Generate
Reference
message
debug-link
Transmit
SHdebug
debug-link link
Receive
SuperHyway
Master
SuperHyway
JTAG TAP
controller
Calculate
address offsets
SHdebug link
JTAG port
• Determine the destination of trace messages received from the watchpoint
controller (WPC) in the CPU core, or from either of the bus analyzers.
• Provide FIFO buffering for trace messages awaiting transmission to a tool or
writing to target memory trace buffer.
• Send trace messages to a tool using either the SHdebug link or the JTAG debug
interface.
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug 05-SA-10003 v1.0