25.02.2015 Views

SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

SHOW MORE
SHOW LESS

You also want an ePaper? Increase the reach of your titles

YUMPU automatically turns print PDFs into web optimized ePapers that Google loves.

PRELIMINARY DATA<br />

Debug module 101<br />

DM.TRCTL<br />

0x100040<br />

Field Bits Size Volatile? Synopsis Type<br />

FF_STATUS [7:6] 2 ✓ DM FIFO status RO<br />

Operation<br />

When read<br />

When written<br />

HARD reset<br />

Indicates the status of the DM FIFO. When the trace destination is<br />

programmed as “DM FIFO trace hold” mode (destn == 0b00) or<br />

“Circular DM FIFO” mode (destn == 0b11), this indicates whether<br />

there are trace messages waiting to be read. In “Trace link mode” or<br />

“Trace buffer mode”, this indicates whether there are trace<br />

messages still waiting to be written to the selected trace destination.<br />

Note:<br />

These status <strong>bit</strong>s do not show whether there are<br />

any WPC watchpoint hits waiting in the capture<br />

buffer. Depending on the programming of the DM<br />

action registers, these may cause new trace<br />

messages to be generated later.<br />

Value - Description<br />

0b00: DM FIFO contains some trace data.<br />

0b01: DM FIFO is empty.<br />

0b10: DM FIFO is full.<br />

0b11: Undefined<br />

Returns current value<br />

Ignored<br />

0b01<br />

Table 31: DM.TRCTL definition<br />

D R A FT<br />

05-SA-10003 v1.0<br />

<strong>SuperH</strong>, Inc.<br />

<strong>SH</strong>-5 <strong>System</strong> <strong>Architecture</strong>, <strong>Volume</strong> 3: Debug

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!