SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
202 SHdebug link
3.2.4 Clocking
The data provided by the SH-5 on the DM_OSYNC and DM_OUT[3:0] pins is stable on the
rising edge of DM_CLKOUT.
The SH-5 debug module divides down the bus clock to provides the DM_CLKOUT clock
source for the SHdebug link. The divider has a power-on default value of 0xFFFF,
giving a SHdebug link clock frequency of approximately 3 kHz with a bus clock
speed of 200 MHz. The divider is a field in memory-mapped register DM.CLKOUTDIV,
which can be changed by host debug software. Debug software must have knowledge
of the bus clock frequency and the maximum operating speed of the debug adapter
before changing the divider value.
In the initial SH-5 evaluation device implementation, the divider cannot be set to
give a division smaller than 2. With a bus clock frequency of 200 MHz, a value of 2
gives a debug-link clock speed of 100 MHz.
In some applications, the CPU and bus clock frequencies can be dynamically
changed by power-management software. By deriving the SHdebug link clock from
bus clock, the SHdebug link clock speed automatically follows changes in bus clock
speed allowing SHdebug link communication to be maintained over any bus speed
range. When SH-5 enters standby state, both the PLL and the master oscillator are
disabled which means that the DM_CLKOUT signal assumes a steady DC level. The
tool should monitor the STATUS0 and STATUS1 signals to determine when SH-5 has
entered standby state.
A tool can issue a command to wake up SH-5 from standby state. However, once the
wake-up command has been issued, it can take up to a millisecond for the PLL to
stabilize and internal clocks to be enabled. The tool must therefore monitor the
STATUS0 and STATUS1 signals and delay any DBUS requests until the chip is
operating normally.
The input clock, DM_CLKIN, is independent of the output clock and is used by the
debug module to extract serial data from the DM_IN and DM_ISYNC pins.
D R A FT
At high clock speeds, the design of the debug adapter must ensure that the
DM_CLKIN, DM_IN and DM_ISYNC signals all have approximately the same I/O pad
delays and interconnect delays. The frequency of DM_CLKIN may be higher or lower
than the frequency of DM_CLKOUT up to the maximum permitted by the electrical
specification of SH-5.
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug 05-SA-10003 v1.0