SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
Scalable parameters 245
Latch name
The latency for the WPC.IAX_CHAIN latches means that the new value is always
visible to the following instruction.
The latency for the WPC.CHAIN_X latch means that the new value is visible between
1 and 4 instructions later than the instruction that causes the change to the latch
value. Put another way, between 0 and 3 following instructions will use the old value
of WPC.CHAIN_X in their precondition checks. The actual number of instructions
involved depends on whether stalls occur in the pipeline (for example, due to
resource or operand dependencies, or delays in instruction fetching).
Latency for DM.CHAIN_x
Delay from WPC
watchpoint Hit (CPU
clocks)
Delay from bus analyzer
watchpoint hit (DM
clocks)
WPC.IAX_CHAIN 1 Not applicable
WPC.CHAIN_X 4 Not applicable
DM.CHAIN_X Not specified - see below. 1
Latch name
DM.CHAIN_TRIGIN
Cycles from pin assertion and chain latch state change
(DM Clocks)
3 to 4 (depending on resynchronization)
Table 88: Chain-latch latency
No figures are specified for the latency of DM.CHAIN_X in association with the
watchpoint controller channels. The timing relationship between particular
SuperHyway transactions and particular instructions being executed in the CPU is
partially asynchronous, due to the presence of caches and instruction buffers inside
the CPU core.
D R A FT
There is no general way to specify whether the altering of DM.CHAIN_X by a bus
analyzer hit on a particular SuperHyway transaction will or will not influence the
precondition checks for a particular CPU instruction on the WPC’s IA/IV/OA
channels.
05-SA-10003 v1.0
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug