SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
SHdebug link 211
3.2.1 SHdebug link control registers
3.2.1.1 DM.CLKOUTDIV (debug-link control register)
This register is specified in Table 74. The divider field of this register allows debug
software to change the clock speed of the SHdebug link.
DM.CLKOUTDIV
0x100090
Field Bits Size Volatile? Synopsis Type
DIVIDER [15:0] 16 — SHdebug link clock divider RW
Operation
When read
When written
HARD reset
This register determines the speed of the SHdebug link clock source
(DM_CLKOUT). The input to the divider is bus clock. A value of n
corresponds to a clock division of 2(n+1). The maximum SHdebug
link output clock speed (divider value = 0) is half the speed of bus
clock.
Returns current value
Updates current value. Debug software must ensure that the debug
link and the debug adapter are capable of supporting the selected
clock speed. All communication between SH-5 and the debug
adapter may be lost if the clock speed is set too high.
0xFFFF
— [63:16] 48 — Reserved RES
Operation
Reserved
When read Returns 0
When written
HARD reset 0
Ignored
D R A FT
Table 74: DM.CLKOUTDIV definition
05-SA-10003 v1.0
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug