SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
Reset, panic and debug events 81
Synchronous debug exceptions
The synchronous debug exceptions are shown in Table 26.They are listed in
decreasing order of priority.
DEBUGIA/IV/OA/SS, BREAK: RESVEC/DBRVEC offset 0x100
WP Channel details Exception type EXPEVT
IA Instruction Address DEBUGIA 0x900
IV Instruction Value DEBUGIV 0x920
BRK BRK executed BREAK 0x940
OA Operand Address DEBUGOA 0x960
BRK Single step DEBUGSS 0x980
DEBUGINT - debug interrupts
Table 26: Synchronous debug exceptions
DEBUGINT: RESVEC/DBRVEC offset = 0x200
WP Channel details
Bits of DM.EXP_CAUSE set for
this channel
DM FIFO activity .DM_FIFO_INTERRUPT == 1
PL SuperHyway bus analyzer .PL_INTERRUPT == 1
BRK debug Interrupt .FORCED_DEBUG_INTERRUPT == 1
OA
OA interrupt with data comparison (see Section
1.12.3: Data match registers on page 147)
D R A FT
Table 27: Debug interrupt reasons
.OA_MATCH_INTERRUPT == 1
05-SA-10003 v1.0
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug