SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
SHdebug link 209
3.2.10 Debug-link message examples
IA watchpoint trace message
Clock cycle DM_OSYNC state DM_OUT[0,3] contents
-1 1 Output-Idle
[2:0] == 0b000 (MHDR_IDLE)
[3] = buffer status
0 1 Header [3:0]
[2:0] == 0b010/0b011 (MHDR_DTRC_{BACK/TRIG})
[3] == bit 3 of trace header
1 0 Header [7:4]
2 0 Header [11:8]
3 0 Header [15:12]
4 0 PC Value [3:0]
5 0 PC Value [7:4]
6 0 PC Value [11:8]
7 0 PC Value [15:12]
8 0 PC Value [19:16]
9 0 PC Value [23:20]
10 0 PC Value [27:24]
11 0 PC Value [31:28]
12 1 Output-Idle
[2:0] = 0b000 (MHDR_IDLE)
[3] = Buffer status
D R A FT
Table 72: Trace message example
05-SA-10003 v1.0
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug