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SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

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PRELIMINARY DATA<br />

Scalable parameters 251<br />

DM.VCR<br />

0x000000<br />

Field Bits Size Volatile? Synopsis Type<br />

BOT_MB [55:48] 8 — Bottom memory block RO<br />

Operation<br />

When read<br />

When written<br />

HARD reset<br />

Used to identify bottom memory block<br />

Returns 0x01<br />

Ignored<br />

0x01<br />

TOP_MB [63:56] 8 — Top memory block RO<br />

Operation<br />

When read<br />

When written<br />

HARD reset<br />

Used to identify top memory block<br />

Returns 0x01<br />

Ignored<br />

0x01<br />

4.1.12 Bus analyzer module/<strong>SuperH</strong>yway mapping<br />

The mapping from physical module number to <strong>SuperH</strong>yway module numbers as<br />

used by the PL_MODULE field of DM.WP_PLX_ACTION (Table 20: DM.WP_PLx_ACTION<br />

register definition on page 60) is given below:<br />

DM.PLx_ACTION.pl_<br />

module<br />

Table 90: DM.VCR<br />

DM.PLx_FRZ.freeze_x<br />

<strong>SuperH</strong>yway module<br />

name<br />

0 <strong>bit</strong> 0 S5 CPU 0x0D<br />

D R A FT<br />

1 <strong>bit</strong> 1 DM 0x0C<br />

2 <strong>bit</strong> 2 DMA 0x0E<br />

3 <strong>bit</strong> 3 PCI 0x60<br />

4 <strong>bit</strong> 4 <strong>SuperH</strong>yway socket 0x70<br />

<strong>SuperH</strong>yway<br />

source iD<br />

5 <strong>bit</strong> 5 F_EMI 0x08<br />

Table 91: DM.PLx_ACTION.pl_module/DM.PLX_FRZ.freeze_x/<strong>SuperH</strong>yway module mapping<br />

05-SA-10003 v1.0<br />

<strong>SuperH</strong>, Inc.<br />

<strong>SH</strong>-5 <strong>System</strong> <strong>Architecture</strong>, <strong>Volume</strong> 3: Debug

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