SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
194 WP channel type PL
Note:
If debug interrupt and trace actions are both enabled, the debug interrupt action
described above takes priority. Since the contents of the bus capture buffer are not
automatically sent to the debug module, no trace message is generated.
DM.WP_PLx_CBHDR
where x = channel id
Note that when the PLx channel is not enabled,
the contents of all fields of this register are
undefined.
Field Bits Size Volatile? Synopsis Type
PLINK_DEST [7:0] 8 ✓ SuperHyway transaction header RO
Operation
When read
When written
HARD reset
This register provides access to the header captured in the bus
analyzer capture buffer following a watchpoint hit when debug
interrupt is enabled. This field is the destination specified in the
bus request or response.
Returns current value
Ignored
Undefined
PLINK_OPCODE [15:8] 8 ✓ SuperHyway transaction header RO
Operation
When read
When written
HARD reset
This field is the opcode specified in the bus request or response.
Returns current value
Ignored
Undefined
PLINK_TID [23:16] 8 ✓ SuperHyway transaction header RO
Operation
When read
When written
HARD reset
This field is the transaction ID specified in the bus request or
response.
D R A FT
Returns current value
Ignored
Undefined
Table 69: DM.WP_PLx_CBHDR register definition
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug 05-SA-10003 v1.0