SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
DBUS protocol 235
Store8
Request
OPC[7:0]
ADDR[31:0]
SRC[7:0]
TID[7:0]
MSK[7:0]
DATA[63:0]
Response
R_OPC[7:0]
R_SRC[7:0]
R_TID[7:0]
Opcode Store8 (0x32).
Address, where ADDR[31:24] identifies the module.
ADDR[23:3] specifies the offset within the module.
ADDR[2:0] is not significant.
Source identifier, defined by the system not the module.
Transaction identifier, defined by the module not the system.
Byte significance within word (‘1’ == significant, ‘0’ == not
significant).
See Table 81: DBUS mask/address mapping for big and little
endian modes on page 230.
Data to write.
Response type, either 0x80 for Success, or 0x81 for Failure.
Copy of SRC.
Copy of TID.
D R A FT
05-SA-10003 v1.0
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug