SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
Debug register address map 253
This split denotes the address encoding appropriate for mapping all the WPC
registers into the WPC address space.
Bank
4.2.2 DM registers
Address
Bit 23:20 Bit 14
Offset range
Chain-latches 0b0001 0b0 0x100000 .. 0x103FFF
CPU control 0b0001 0b1 0x104000 .. 0x104018
Event counters 0b0010 0b0 0x200000 .. 0x203FFF
Performance counters 0b0010 0b1 0x204000 .. 0x207FFF
IA and IV WP channels 0b0100 0b0 0x400000 .. 0x403FFF
OA WP channels 0b0100 0b1 0x404000 .. 0x407FFF
Table 92: WPC debug register layout
The basic ordering is DM, WPC. Within each of these there is a regular structure as
shown in Table 92.
Module bank In-bank ordering Offset range
Debug module
(includes bus
analyzer
registers)
Module specific setup and
chain-latches
Event and performance
counters
Registers physically located in
bus analyzer
WP channels, including bus
analyzer registers physically
located in DM
0x100000 .. 0x100080 17
0x200000 .. 0x200018 3
D R A FT
0x400000 .. 0x4000F8
0x800000 .. 0x800248
Number of
64-bit
registers
assigned
16 per
channel, 2
channels
8 per
channel, 10
channels
Table 93: Debug register layout
05-SA-10003 v1.0
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug