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SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

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PRELIMINARY DATA<br />

96 Debug module<br />

Since the chain-latch can be directly set by one WPC watchpoint hit and directly<br />

cleared by a different WPC watchpoint hit, the trigger-out pin can be used to<br />

accurately measure the time between different WPC watchpoint events.<br />

4 The trigger-out pin is connected to the output of the DM.CHAIN_0 chain-latch.<br />

Since the chain-latch can be directly set by one WPC or bus analyzer watchpoint<br />

hit and directly cleared by a different watchpoint hit, the trigger-out pin can be<br />

used to measure the time between different watchpoint events. There are two<br />

main differences between this TRIGGER-OUT function and the one described above<br />

for the WPC.CHAIN_0 chain-latch:<br />

• The DM.CHAIN_0 chain latch can be set or cleared by any bus analyzer or WPC<br />

watchpoint.<br />

• The action logic for DM.CHAIN_0 chain-latch setting/clearing is located at the<br />

output of the capture buffer. If stall-mode is selected, the chain-latch setting/<br />

clearing action will be delayed by an unpredictable amount of time as the<br />

capture buffer fills. If discard-mode is selected, watchpoint hit events will be<br />

discarded when the capture buffer fills and expected chain-latch setting/<br />

clearing actions may not occur.<br />

5 If stall mode is selected, the trigger-out pin goes low during the time that the<br />

CPU is stalled. This allows external equipment connected to the trigger-out pin<br />

to observe CPU stall behavior.<br />

D R A FT<br />

<strong>SuperH</strong>, Inc.<br />

<strong>SH</strong>-5 <strong>System</strong> <strong>Architecture</strong>, <strong>Volume</strong> 3: Debug 05-SA-10003 v1.0

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