SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
Debug register address map 263
DM channel-specific registers
Register name Offset References
IA DM.WP_IA0_PRE 0x800000 Table 15: DM.WP_{IA/OA/
IV}x_PRE register definition
on page 42
DM.WP_IA0_ACTION 0x800008 Table 19: DM.WP_{IA/OA/
IV}x_ACTION register
definition on page 54
DM.WP_IA1_PRE 0x800040 See cross references for
channel WP_IA0.
DM.WP_IA1_ACTION
0x800048
DM.WP_IA2_PRE
DM.WP_IA2_ACTION
DM.WP_IA3_PRE
DM.WP_IA3_ACTION
0x800080
0x800088
0x8000C0
0x8000C8
OA DM.WP_OA0_PRE 0x800100 See cross references for
channel WP_IA0.
DM.WP_OA0_ACTION
0x800108
DM.WP_OA1_PRE
DM.WP_OA1_ACTION
0x800140
0x800148
IV DM.WP_IV0_PRE 0x800180 See cross references for
channel WP_IA0.
DM.WP_IV0_ACTION
0x800188
DM.WP_IV1_PRE
DM.WP_IV1_ACTION
0x8001C0
0x8001C8
D R A FT
FPF DM.WP_FPF_PRE 0x800280 Table 17: DM.WP_FPF_PR
E register definition on
page 46
Table 94: Register map and references
05-SA-10003 v1.0
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug