SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
32 CPU control
WPC.CPU_CTRL_ACTION
0x104000
Field Bits Size Volatile? Synopsis Type
— [63:2] 62 — Reserved RES
Operation
Reserved
When read Returns 0
When written
HARD reset 0
Ignored
Table 10: WPC.CPU_CTRL_ACTION register definition
If the value CPU_CTRL_OP_DEBUGRESET is written to WPC.CPU_CTRL_ACTION twice or
more in succession, the second and subsequent writes will be ignored. To perform a
second DEBUGRESET event, the WPC.CPU_CTRL_ACTION register must have a different
value (such as CPU_CTRL_OP_RESUME) written to it before writing
CPU_CTRL_OP_DEBUGRESET for the second time. In particular, it is assumed that the
bootstrap code entered after a DEBUGRESET event will write CPU_CTRL_OP_RESUME
to WPC.CPU_CTRL_ACTION as one of its steps.
In contrast, each write of the value CPU_CTRL_OP_CPURESET to the
WPC.CPU_CTRL_ACTION register will cause a CPURESET event, regardless of the
previous value written to the register.
D R A FT
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug 05-SA-10003 v1.0