SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

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PRELIMINARY DATA 174 WP channel type WPC_PERF WPC.WP_WPC_PERFx_MATCH_TYPE where x = channel ID Field Bits Size Volatile? Synopsis Type INSTR_BRANCH_ STALL 20 1 — Instruction branch stall RW Operation When read When written HARD reset A branch caused a pipeline stall (or NOP execution) as the instruction following the branch was not available in the instruction queue), however the branch target address was available (so this match type is distinct from TARGET_ADDRESS_STALL). Results in either 0 or N increments per instruction (depending on number of stall cycles for that instruction’s execution). Returns current value Updates value Undefined STALL_CYCLE 21 1 — Stall cycle RW Operation When read When written HARD reset A stall cycle occurred - this covers all cases of stall. Results in either 0 or N increments per instruction (depending on number of stall cycles for that instruction’s execution). Returns current value Updates value Undefined CPU_CYCLE 22 1 — CPU Clock Cycle RW Operation When read When written A CPU clock cycle occurred. When this field is set to ‘1’, the match will occur on every CPU clock cycle regardless of all other performance monitoring causes. This can be used to count CPU clock cycles. D R A FT Returns current value Updates value HARD reset Undefined Table 60: WPC.WP_WPC_PERFx_MATCH_TYPE register definition SuperH, Inc. SH-5 System Architecture, Volume 3: Debug 05-SA-10003 v1.0
PRELIMINARY DATA WP channel type WPC_PERF 175 WPC.WP_WPC_PERFx_MATCH_TYPE where x = channel ID Field Bits Size Volatile? Synopsis Type — [63:23] 41 — Reserved RES Operation Reserved When read Returns 0 When written HARD reset 0 Ignored Table 60: WPC.WP_WPC_PERFx_MATCH_TYPE register definition D R A FT 05-SA-10003 v1.0 SuperH, Inc. SH-5 System Architecture, Volume 3: Debug
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PRELIMINARY DATA SuperH TM (SH) 64-
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PRELIMINARY DATA Contents Preface 9
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PRELIMINARY DATA 5 1.8.11 DM.TRBUF
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PRELIMINARY DATA 7 3.2.5 Pin state
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PRELIMINARY DATA Preface This docum
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PRELIMINARY DATA Debug/trace archit
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PRELIMINARY DATA Overview of debug
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PRELIMINARY DATA Key concepts 15 Th
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PRELIMINARY DATA Key concepts 17 Ac
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PRELIMINARY DATA Key concepts 19 1.
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PRELIMINARY DATA Key concepts 21 1.
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PRELIMINARY DATA Key concepts 23 La
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PRELIMINARY DATA Key concepts 25 {W
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PRELIMINARY DATA Key concepts 27 If
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PRELIMINARY DATA Key concepts 29 Re
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PRELIMINARY DATA CPU control 31 1.3
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PRELIMINARY DATA CPU control 33 1.3
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PRELIMINARY DATA Watchpoint channel
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PRELIMINARY DATA Debug event action
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PRELIMINARY DATA WP channel matchin
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PRELIMINARY DATA Reset, panic and d
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PRELIMINARY DATA Debug module 85 DM
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PRELIMINARY DATA Debug module 87
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PRELIMINARY DATA Debug module 89 Wh
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PRELIMINARY DATA Debug module 91 St
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PRELIMINARY DATA Debug module 93 Mu
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PRELIMINARY DATA Debug module 95 1.
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PRELIMINARY DATA Debug module 97 1.
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PRELIMINARY DATA Debug module 99 DM
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PRELIMINARY DATA Debug module 101 D
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PRELIMINARY DATA Debug module 107 1
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PRELIMINARY DATA Debug module 113
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PRELIMINARY DATA Debug module 117 1
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PRELIMINARY DATA Debug protocols an
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PRELIMINARY DATA Debug protocols an
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Page 179 and 180: PRELIMINARY DATA SuperHyway bus ana
Page 181 and 182: PRELIMINARY DATA SuperHyway watchpo
Page 183 and 184: PRELIMINARY DATA Address comparison
Page 185 and 186: PRELIMINARY DATA Freezing bus maste
Page 187 and 188: PRELIMINARY DATA WP channel type PL
Page 199 and 200: PRELIMINARY DATA External debug int
Page 201 and 202: PRELIMINARY DATA SHdebug link 201 3
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Page 207 and 208: PRELIMINARY DATA SHdebug link 207 D
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PRELIMINARY DATA Trigger functions
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PRELIMINARY DATA DBUS protocol 227
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PRELIMINARY DATA Implementation spe
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PRELIMINARY DATA Scalable parameter
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PRELIMINARY DATA Debug register add
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PRELIMINARY DATA Index A Actions 13
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PRELIMINARY DATA 267 244, . . . . .
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PRELIMINARY DATA 269 158-160, 166-1
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