SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
WP channel type WPC_PERF 165
Supported actions (determined by ff_thresh field of
DM.TRCTL)
INTERRUPT: Standard Event Handling sequence is followed. The RESVEC/DBRVEC
offset is 0x200 (to denote a DEBUGINT event).
DM.EXP_CAUSE.DM_FIFO_INTERRUPT is set to 1.
The trace information present in the FIFO can be emptied one entry at a time, this
is described in Section 1.8.13: DM.FIFO_0/DM.FIFO_1/DM.FIFO_2 (FIFO port
register) on page 112.
1.18 WP channel type WPC_PERF
SH-5 has four performance counters, two located within the WPC and two located in
the DM.
A WPC performance counter is incremented when either of the following types of
events occur:
• A WPC watchpoint hit occurs and the watchpoint has its action_pcount field == 1
and pcount_id field selecting a specific performance counter.
• Whenever a CPU core event specified by fields of the
WPC.WP_PERFX_MATCH_TYPE occurs and the conditions specified by fields of the
WPC.WP_PERFX_PRE exist.
One register per WPC_PERF channel is used to define the match conditions. The WPC
performance counter channels do not have a WPC.WP_PERFX_ACTION register, they
have an implicit action to increment the corresponding WPC performance counter.
For example, the WPC.WP_PERF0 channel increments the WPC.PCOUNT_VALUE_0
counter.
The specified match conditions are detected at different blocks of the CPU, and at
different stages of the CPU pipeline. Thus the exact timing relationship between
different match conditions is implementation dependant.
D R A FT
On each cycle, the match conditions are “OR”ed together and processed, yielding
either 0 or 1 increments per cycle. The descriptions of the individual filters (in
Table 60) specify whether this results in either 0..1 or 0..N increments per
instruction.
05-SA-10003 v1.0
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug