25.02.2015 Views

SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

SHOW MORE
SHOW LESS

Create successful ePaper yourself

Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.

PRELIMINARY DATA<br />

Debug module 115<br />

DM.FIFO_REQ<br />

0x100070<br />

Field Bits Size Volatile? Synopsis Type<br />

FF_READ_<br />

REQ<br />

0 1 ✓ DM FIFO transfer request RW<br />

Operation<br />

When read<br />

When written<br />

HARD reset 0<br />

In “DM FIFO trace hold” mode or “circular DM FIFO” mode, this is<br />

one of the fields used to transfer data from the DM FIFO to the DM<br />

FIFO port registers.<br />

Undefined<br />

Value - Description<br />

0: No action<br />

1: Initiates a transfer of the oldest trace message in the DM FIFO to<br />

the DM FIFO port registers.<br />

— [63:1] 63 — Reserved RES<br />

Operation<br />

Reserved<br />

When read Returns 0<br />

When written<br />

HARD reset 0<br />

Ignored<br />

Table 36: DM.FIFO_REQ definition<br />

D R A FT<br />

05-SA-10003 v1.0<br />

<strong>SuperH</strong>, Inc.<br />

<strong>SH</strong>-5 <strong>System</strong> <strong>Architecture</strong>, <strong>Volume</strong> 3: Debug

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!