SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
WP channel type IA 141
1.11.2 Address comparison
The address comparison is performed using the effective address supplied to the
instruction (known as Aeffective). When the MMU is enabled, this is an effective
address. When the MMU is disabled, this is a physical address.
The comparisons are unsigned. If the start/end address range straddles the
unimplemented part of the effective address space (that is, it contains addresses in
the range [2 (neff - 1) , 2 (64 - neff - 1) ) where neff is the number of implemented effective
address bits, the behavior is architecturally undefined. If this type of ‘stradding’
behavior is required, two IA channels must be programmed, each one limited to
addresses in a single region of the implemented address space.
1.11.3 SHcompact behavior
SH-5 may implement SHcompact instruction execution by actual execution of a
sequence of SHmedia instructions. In such implementations, IA watchpoint
matches are made against the address of the single SHcompact instruction (as the
sequence of SHmedia instructions generated have no PC address).
1.11.4 Event specifics
Source CPU
Reason: Fetch of an instruction at an address which is within an enabled IA
watchpoint.
Undefined behavior
The following operations of the IAx registers are undefined:
• Writing to WPC.WP_IAX_{PRE/MATCH/ACTION}, DM.WP_IAX_{PRE/ACTION} when the
WP channel is enabled.
D R A FT
Supported fields in WPC.WP_IAx_PRE:
BASIC_ENABLE, ASID_ENABLE, ASID_VALUE, ISAMODE_ENABLE, SR_MD_ENABLE,
ECOUNT_ENABLE, ECOUNT_ID, CHAIN_ENABLE, CHAIN_ID
05-SA-10003 v1.0
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug