SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
WP channel type WPC_PERF 167
WPC.WP_WPC_PERFx_MATCH_TYPE
where x = channel ID
Field Bits Size Volatile? Synopsis Type
ICACHE_MISS 2 1 — Instruction Cache Miss RW
Operation
When read
When written
HARD reset
An instruction fetch missed the Instruction cache.
This excludes prefetches (PREFI).
Results in either 0 or 1 increments per instruction.
Returns current value
Updates value
Undefined
OTLB_MISS 3 1 — OTLB miss RW
Operation
When read
When written
HARD reset
Operand access failed (due to a lack of an data TLB
translation).
Results in either 0 or 1 increments per instruction.
Returns current value
Updates value
Undefined
OCACHE_ACCESS 4 1 — Operand Cache Access RW
Operation
When read
When written
HARD reset
See Section 1.18.2: Operand cache access types on
page 176.
Results in either 0 or 1 increments per instruction.
Returns current value
Updates value
D R A FT
Undefined
Table 60: WPC.WP_WPC_PERFx_MATCH_TYPE register definition
05-SA-10003 v1.0
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug