SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
184 Bus watchpoint hit action
2.5 Bus watchpoint hit action
When a bus watchpoint is enabled and a hit occurs, the bus analyzer signals the
debug module that the hit has occurred and also optionally captures the bus
transaction in a bus capture buffer. Action conditions for the PL watchpoint
channels are the same as for other watchpoint channels, but additionally include the
inhibition of the originating bus module from generating further bus transactions,
that is, freeze the source.
Because of the pipelined nature of bus arbitration, it is not possible to immediately
“freeze” a bus master following a bus analyzer watchpoint hit.
This ability to “freeze” the originating bus master applies only if the
DM.WP_PLX_CTRL.SRC field identifies the bus master uniquely.
Debug interrupt actions
When bus analyzer debug interrupt is not enabled, but trace is enabled and a
watchpoint hit occurs, the contents of the bus capture buffer are immediately sent to
the debug module so that a trace message can be generated. The capture buffer is
then available to capture another watchpoint hit token.
However, when a bus analyzer has debug interrupt enabled and a watchpoint hit
occurs, the contents of the bus capture buffer are not sent to the debug module.
Instead, a 1-bit register, DM.WP_PLS_EXCTRL.CBUF_FREEZE, is set by the watchpoint
hit and stops the capture buffer from being overwritten by another watchpoint hit.
The debug event handler is able to directly read the bus capture buffer to get details
of the bus transaction which caused the watchpoint hit and can then re-enable the
capture buffer by clearing DM.WP_PLS_EXCTRL.CBUF_FREEZE.
D R A FT
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug 05-SA-10003 v1.0